Logic Design Verification Engineer
Petach Tikva, Israel.APPLY
- Prepare design verification plan based on design specifications.
- Develop verification test benches, and high-coverage stimulus vectors.
- Work closely with the hardware / software design team to ensure timely delivery of quality designs.
- Sc in Electrical Engineering or Computer Engineering or Computer Science - a must.
- Experience with C / C++ - an advantage.
- At least 2 years of relevant experience as a Logic Design Verification Engineer.
- Familiarity with verification environments, SystemVerilog – an advantage.