Logic Design Verification Engineer
- Prepare design verification plan based on design specifications.
- Develop verification test benches and high-coverage stimulus vectors.
- Work closely with the hardware/software design team to ensure timely delivery of quality designs.
- Sc in Electrical Engineering or Computer Engineering or Computer Science - a must.
- Familiarity with verification environments, SystemVerilog – a must.
- At least 5 years of relevant experience as a Logic Design Verification Engineer.
- Experience with C / C++ - an advantage.